Test bench development, Directed/constrained random test generation, Failure analysis and resolution, and coverage analysis.
• Experience with PCIe/CXL, AXI, Ethernet
• Experience with FPGA emulation
• Prior experience working with Ethernet NIC or Switch ASICs
What we are looking for in this position:
• Advanced knowledge of standard ASIC design and verification flows, simulation and test bench development
• Advanced knowledge of System Verilog and the UVM methodology
• Solid verification skills in problem-solving, constrained random testing, coverage closure, gate-level simulations, X propagation.
• Experience writing scripts in languages such as Perl or Python
• Team player with excellent communication skills and the desire to take on diverse challenges